The present invention relates generally to integrated circuits and, more particularly, to packaging integrated circuits.
Conventionally, an integrated circuit package provides for electrical connections from an integrated circuit chip to external conductors, and for protection of the chip from the external environment. Large integrated circuits, for example, Application Specific Integrated Circuits (ASICs) used in telecommunications and other applications may dissipate powers in excess of several watts. Consequently, it may be necessary to provide an integrated circuit package with a heat sink whereby the integrated circuit chip is in thermal contact with a conductive substrate of thermally conductive metal or alloy having an exposed surface for dissipation of heat.
One type of package which is now of significant interest for high lead count integrated circuits, e.g. ASICs for telecommunications applications, is a Ball Grid Array (BGA) package. The terminals take the form of arrays of solder balls. The solder balls are attached by solder reflow to pads on a substrate, which allow for a high density of compact and reliable interconnections. The BGA package body may comprise a polymer, e.g. polyimide, or a ceramic dielectric body. Optionally a BGA package may include a heat spreader, for example, in the form of a heat conductive slug, which is typically copper, or another thermally conductive metal or alloy.
A schematic diagram of a known commercially available ball grid array package for an integrated circuit is shown in FIG. 3. The package 10 for an integrated circuit 12 includes a thermally conductive heat spreader 14, which is typically a layer of metal. The metal is typically thin sheets or a thick slug of a metal such as copper. The integrated circuit 12 is bonded by a thermally conductive die attach adhesive medium 13 to the heat spreader 14.
Bond pads 16 of the integrated circuit are electrically connected via electrically conductive leads 18 to conductive traces defined by electrical conductive layers 16, 20, and 22 within the substrate of the package. The substrate includes dielectric layers 24, 26, and 27 forming a structure similar to that used in printed wiring board technology. The heat spreader 14 is bonded to one side of the substrate. On the opposite side of the substrate there is provided a conductive layer 28 defining conductive traces on which is disposed an array of solder balls 30. Conductive through holes 31 extend through the dielectric layers 24, 26, and 27 forming the substrate to provide for electrical interconnections between the solder balls 30 and the contact pads 16 of the integrated circuit chip. A layer of encapsulatant 32 encloses and protects the integrated circuit chip 12 and the bonding wires 18.
The package is interconnected to the motherboard 38 via ball bonds formed by thermal reflow of the solder balls 30 to form connections to corresponding individual contact pads 36 on the substrate 10. This package has one or more levels of metal interconnections, e.g. 16, 20 and 22, in a cavity down configuration. In this configuration, however, a number of different levels are provided for power, ground, and signal connections. Each additional level in the substrate increases the cost of the package. Thus, it would be desirable to reduce the number of levels.
The present invention provides an integrated circuit package where the integrated circuit chip is mounted on a conductive slug and electrically coupled to the conductive slug. Besides acting as a heat spreader, the conductive slug may also function as a ground plane. This reduces the need for additional conductive layers and plated through hole connections for forming connections to, for example, ground. As a result, the conductive paths in the internal ground planes are not necessarily cut off by the plated through holes used for interconnecting ground connections thus avoiding some of the electrical performance degradation suffered by prior techniques. In addition, the invention allows more signals to be added and/or the size of the integrated circuit chip to be reduced to enhance electrical performance. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.